1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory for storing multivalued data by an electrical rewrite.
2. Description of the Related Art
In recent years, a nonvolatile semiconductor memory, particularly, a flash memory can electrically rewrite data and can hold the data also in a state in which a power supply is turned OFF. Therefore, a large number of nonvolatile semiconductor memories have been used as memories for data storage of portable apparatuses such as a cell phone, a digital camera and a silicon audio player.
These portable apparatuses deal with images, animations and music data having a large data volume. In the nonvolatile semiconductor memory, therefore, it has been further demanded to implement an increase in a capacity and a reduction in a cost. Examples of a nonvolatile semiconductor memory capable of implementing the increase in a capacity and the reduction in a cost include an NAND type flash memory.
In order to implement the increase in a capacity and the reduction in a cost still more, moreover, the NAND type flash memory using a multivalued technique for storing data having 2 bits or more in one memory cell has been studied and developed vigorously.
For example, there has conventionally been proposed a nonvolatile semiconductor memory having 2-bit data in one memory cell, that is, four different threshold voltages in one memory cell (see JP-A-2001-93288).
FIG. 12 is a diagram showing a relationship between a threshold voltage distribution of a memory cell in the nonvolatile semiconductor memory described in JP-A-2001-93288 and data, and writing and reading methods. FIG. 13 is a diagram showing a relationship between data of the memory cell in the nonvolatile semiconductor memory described in JP-A-2001-93288 and write and read data.
As shown in FIGS. 12 and 13, a “state 0” to a “state 3” are defined in the ascending order of the threshold voltage of the memory cell. When an erasure is carried out, the data of the memory cell are brought into the “state 0”. By a writing operation, consequently, the memory cell is set to be the “state 1” to the “state 3” in which the threshold voltage is high.
Data on different pages are stored in the 2-bit data to be stored in one memory cell. More specifically, data on first and second pages having different page addresses from each other are stored. In the 2-bit data to be stored in the “state 0” to the “state 3”, moreover, the data on the first page are assigned to an LSB (Least Significant Bit) side and the data on the second page are assigned to an MSB (Most Significant Bit) side.
The threshold voltage in the “state 0” to the “state 3” and the data of the memory cell are assigned in such a relationship that the “state 0” is data “11”, the “state 1” is data “10”, the “state 2” is data “00” and the “state 3” is data “01”.
Thus, the nonvolatile semiconductor memory in which the data are assigned executes a writing operation, that is, an operation for first writing the data on the first page and then writing the data on the second page in the case in which the data are written (programmed) to the memory cell.
For example, it is assumed that the threshold voltage of the memory cell is set into the “state 0” to be an erasing state in an initial condition. As described above, the data on the first page are first written to the memory cell. In the case in which the write data are “1”, accordingly, the threshold voltage of the memory cell is maintained in the “state 0”. In the case in which the write data are “0”, moreover, the threshold voltage of the memory cell is brought into the “state 1”.
Next, the data on the second page are written to the memory cell. At this time, in the case in which data “0” are written from an outside to the memory cell in which the threshold voltage is brought into the “state 1” by a writing operation for the first page, the threshold voltage of the memory cell is brought into the “state 2”. In the case in which the data “0” are written from the outside to the memory cell in which the threshold voltage is maintained in the “state 0” by the writing operation for the first page, the threshold voltage of the memory cell is brought into the “state 3”.
In the case in which the data “1” are written from the outside to the memory cell in which the threshold voltage is brought into the “state 1” by the writing operation for the first page, furthermore, the threshold voltage of the memory cell is maintained in the “state 1”. In the case in which the data “1” are written from the outside to the memory cell in which the threshold voltage is maintained in the “state 0” by the writing operation for the first page, moreover, the threshold voltage of the memory cell is maintained in the “state 0”.
On the other hand, in the case in which the data stored in the memory cell are read, the data to be read are “1” if the threshold voltage of the memory cell is set into the “state 0” or the “state 1” and are “0” if the threshold voltage of the memory cell is set in the “state 2” or the “state 3” when the data on the second page are to be read.
In the case in which the data on the second page are read, accordingly, whether the threshold voltage of the memory cell is set into the “state 1” or less or the “state 2” or more can be decided by only one reading operation. More specifically, by setting a word line voltage B for reading the second page to be a threshold, it is decided whether the threshold voltage of the memory cell is set into the “state 1” or less or the “state 2” or more.
On the other hand, in the case in which the data on the first page are read, the data to be read are “1” if the threshold voltage of the memory cell is set into the “state 0” or the “state 3” and are “0” if the threshold voltage of the memory cell is set into the “state 1” or the “state 2”. In the case in which the data on the first page are read, accordingly, it is necessary to carry out two deciding operations in total including a decision whether the threshold voltage of the memory cell is set into the “state 0” or the “state 1” or more and a decision whether the threshold voltage of the memory cell is set into the “state 2” or less or the “state 3”. Therefore, it is necessary to carry out two reading operations in total.
More specifically, it is decided whether the threshold voltage of the memory cell is set into the “state 0” or the “state 1” or more by setting, as a threshold, a reading word line voltage A of the first page and it is decided whether the threshold voltage of the memory cell is set into the “state 2” or less or the “state 3” by setting, as a threshold, a reading word line voltage C of the first page.
In the nonvolatile semiconductor memory described in JP-A-2001-93288, thus, the number of times of read is one in the case in which the second page is read and is two in the case in which the first page is read in the operations for reading the first and second pages. Thus, it is possible to carry out the reading operation in the number of times of read which is two at a maximum. Consequently, it is possible to perform a high speed reading operation.
[Non-Patent Document 1] 2005 IEEE International Solid-State Circuits Conference ┌2.2 An 8 Gb Multi-Level NAND Flash Memory with 63 nm STI CMOS Process Technology┘
[Non-Patent Document 2] 2004 IEEE International Solid-State Circuits Conference ┌2.7 A 3.3V 4 Gb Four-Level NAND Flash Memory with 90 nm CMOS Technology┘
On the other hand, referring to a writing operation, the threshold voltage of the memory cell carries out a transition from the “state 0” to be an erasing state (data “11”) to the “state 3”, that is, to a state in which the data on the first page are “1” and the data on the second page are “0” (data “01”) in the case in which an operation for writing the second page to the memory cell set in the erasing state is first performed and write data are “0”.
In the case in which an operation for writing the first page is carried out and the write data are “0”, subsequently, it is necessary to drop the threshold voltage of the memory cell in order to assign preset data, and furthermore, to cause the threshold voltage of the memory cell to carry out a transition from the “state 3” to the “state 2”, that is, a transition to a state 2 (data “00”) in which the data on the first page is “0” and the data on the second page is “0”.
Referring to the operation for dropping the threshold voltage of the memory cell, however, a flash memory is only permitted to carry out an erasing operation for collectively dropping a threshold voltage on a unit of a block in respect of a structure of a circuit and cannot set a threshold voltage of only a specific memory cell into a low state. Accordingly, the nonvolatile semiconductor memory described in the JP-A-2001-93288 cannot carry out the writing operation in order of the second page and the first page but can carry out the writing operation only in order of the first page and the second page.
Thus, restrictions on the writing order in which the writing operation cannot be executed in optional page order forcibly cause an apparatus mounting the nonvolatile semiconductor memory thereon and a control apparatus for controlling the nonvolatile semiconductor memory to carry out a complicated rewrite control. Consequently, there is generated the case in which an address space of the nonvolatile semiconductor memory cannot be used efficiently.